Method of producing and arrangement containing self-amplifying dynamic MOS transistor memory cells

ABSTRACT

To produce an arrangement containing self-amplifying dynamic MOS transistor memory cells which each comprise a selection transistor, a memory transistor and a diode structure, the selection transistor and the memory transistor being connected in series via a common nodal point and the diode structure being connected between the common nodal point and the gate electrode (10) of the memory transistor, the selection transistor and the memory transistor are formed as vertical MOS transistors. For this purpose a vertical sequence of suitably doped zones (2, 3, 4) in which trenches (5, 6) are produced and which are provided with gate dielectric (7, 8) and gate electrode (9, 10) is produced, in particular, by LPCVD epitaxy or by molecular-beam epitaxy.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to a method produce anarrangement containing self-amplifying dynamic MOS transistor memorycells which each comprise a selection transistor, a memory transistorand a diode structure.

2. Description of the Related Art

With increasing storage density per chip from one memory generation tothe next, the area of dynamic semiconductor memory cells is beingcontinuously reduced. For this purpose, from the 4 Mbit memorygeneration onwards, three-dimensional structures are necessary. From the64 Mbit memory generation onwards, the memory capacity has reached avalue which can hardly still be reduced, with the result that anapproximately constant capacity has to be formed on a reduced cell area.This results in an appreciable technological expenditure. It istherefore necessary to impose on an improved dynamic semiconductormemory cell the requirement that the level of the signal charge is notdetermined by the size of the memory capacity.

This requirement is fulfilled by memory cells in which the signal chargeis provided not by a storage capacitor but by a supply-voltage source.In this case, it is sufficient to store in the storage capacitor only asmaller charge which, when the memory cell is read out, activates aswitching element so that a conducting connection is made between thesupply-voltage source and the bit line. Such memory cells are referredto as self-amplifying memory cells or gain memory cells.

The publication by T. Tsuchiya et al., IEEE Electr. Dev. Lett. (1982),EDL-3, page 7 and T. Tsuchiya et al., IEEE Trans. Electr. Dev. (1982),ED-29, page 1713, disclose a self-amplifying memory cell containing abarrier-layer field-effect transistor. In this type of memory cell, thestored charge controls the extent of a space-charge zone of a p-njunction. If the cell is charged, the space-charge zone is enlarged tosuch an extent that it constricts the current channel between voltagesource and bit line. If, on the other hand, no charge is stored in thecell, the current channel is not constricted and current is able to flowfrom the voltage source to the bit line. In this type of cell, thesemiconductor region forming the p-n junction and the current channelcan only have low tolerances so as to ensure both adequate current flowand also reliable blocking during corresponding charging. In addition,an additional line is needed to write the information.

The publication by K. Terada et al., IEEE Trans. Electr. Dev. (1982),ED-29, page 1301, discloses a self-amplifying memory cell containing aDMOS transistor. In this case, a planar MOS transistor and a DMOStransistor are integrated with one another. The charge representing theinformation is stored in the substrate of the DMOS transistor. Dependingon the charging state of the substrate, the DMOS transistor assumes twodifferent threshold voltages. In this type of cell, positive andnegative voltages are necessary on the word line. Furthermore, thelevels must be adjusted very precisely in order to be able todifferentiate between a logic "zero" and "one" during reading-out.

The publication by T. N. Blalock et al., Symp. VLSI Circuits Dig. Tech.Pap. (1990), page 13, discloses a two-transistor memory cell which hasbeen developed from the three-transistor cell and in which the thirdtransistor, which is used to read out, is omitted. Instead, the state ofthe memory transistor is scanned by lines arranged in matrix fashion.This type of cell requires four lines, which have to be routed over thecell array in the form of a double matrix. Four contacts are necessaryfor each cell, which limits the reduction in the cell area. Furthermore,the source and drain regions of the two transistors cannot be formed bya common doped zone, as would be necessary for a small cell area.

A self-amplifying memory cell containing an MOS transistor and a bipolartransistor is disclosed, for example, by K. Sunouchi et al., in thepublication IEDM Tech. Dig. (1991), page 465. In this memory cell, theamplifying action of a parasitic bipolar transistor is exploited. As aresult, the required capacity of the storage capacitor can be reducedappreciably. Since the bipolar transistor is a parasitic element, itcannot be formed with the reproducibility required for memory cells. Theintegration of a bipolar transistor in the memory cell with minimumdesign rules would result in a comparatively large cell area.

The international published patent application WO 92/012887 and thepublication by W. H. Krautschneider et al., Proc. ESSDERC (1991), page367, disclose a self-amplifying dynamic MOS transistor memory cell whichcomprises a selection transistor and a memory transistor. In this memorycell, the charge is stored in the gate capacitance and sourcecapacitance of the memory transistor. The two transistors are connectedin series and have a common drain/source zone. The common drain/sourcezone is connected to the gate electrode of the memory transistor via adiode structure. During reading-out, the memory transistor is turned onin accordance with the stored information and thereby closes a currentpath from the supply voltage to the bit line. In this type of cell,selection transistor and memory transistor are connected in series sothat a special line is not required to read out the signal.

SUMMARY OF THE INVENTION

The present invention is based on the problem of providing a method ofproducing an arrangement containing self-amplifying dynamic MOStransistor memory cells, with which method the area of the memory cellscan be reduced further.

According to the invention, this problem is solved by a method in whichan arrangement containing self-amplifying dynamic MOS transistor memorycells is produced,

in which a silicon substrate is provided with a vertical sequence ofdoped zones which comprises at least a first doped zone, a second dopedzone disposed thereon and a third doped zone disposed thereon for sourcezone, channel zone and drain zone of vertical MOS transistors,

in which a first trench and a second trench are etched which extend downinto the first zone and which traverse the second zone and the thirdzone,

in which the surface of the first trench is provided with a first gatedielectric and the surface of the second trench is provided with asecond gate dielectric,

in which a first gate electrode is formed in the first trench and asecond gate electrode is formed in the second trench,

in which a third trench which cuts through the first doped zone, thesecond doped zone and the third doped zone is produced between the firsttrench and the second trench,

in which the third trench is provided with a first isolation structureat least in the region of the first doped zone and of the second dopedzone, in which those parts of the third doped zone that are separated bythe third trench are electrically interconnected by an interconnectstructure,

in which a diode structure is produced whose one terminal is connectedin an electrically conducting manner to the third doped zone and whoseother terminal is connected in an electrically conducting manner to thatof the second gate electrode. Further developments of the inventionprovide that the silicon substrate is doped with a first conductivitytype, α silicon layer doped with a second conductivity type opposite tothe first is grown epitaxially on the silicon substrate to form thefirst doped zone, a silicon layer doped with the first conductivity typeis applied by LPCVD epitaxy or by molecular-beam epitaxy to form thesecond doped zone, and a silicon layer doped with the secondconductivity type is applied by LPCVD epitaxy or by molecular-beamepitaxy to form the third doped zone. Preferably, the diode structure isformed as a Schottky diode. The diode structure may be formed as an n+-p diode.

In one embodiment, the second gate electrode is formed from dopedpolysilicon, a doped polysilicon structure is produced which, with thesecond gate electrode, is the diode structure, and the doped polysiliconstructure is connected in an electrically conducting manner to the thirddoped zone.

The further detail, the second gate electrode is produced in the secondtrench in a height essentially corresponding to the level of the seconddoped zone, the doped polysilicon structure is produced in the secondtrench above the second gate electrode, the surface of the dopedpolysilicon structure is provided with a metal silicide layer, a dopedpolysilicon strip is produced in which the metal silicide layer and thethird doped zone overlap at least partly in each case.

A preferred method provides that a diffusion-barrier layer is producedbetween the second gate electrode and the doped polysilicon structure.

The dopant concentration in the first doped zone and in the third dopedzone is adjusted in the range greater than or equal to 10¹⁹ cm⁻³, thedopant concentration in the second doped zone is adjusted in the rangeless than or equal to 10¹⁸ cm⁻³, and the first gate dielectric and thesecond gate dielectric are formed by thermal oxidation at 700° to 800°C.

The interconnect structure may be formed by means of the third trenchcomposed of doped polysilicon of the same conductivity type as the thirddoped zone.

A multiplicity of memory cells are disposed in matrix fashion in thesilicon substrate, the first trench, the second trench and the thirdtrench are each formed as parallel strips, there is produced, inside thefirst trench, a fourth trench which cuts through the first doped zoneand in which a second isolation structure is formed which isolates atleast the parts of the first doped zone on either side of the fourthtrench from one another, there is produced, inside the second trench, afifth trench which cuts through the first doped zone and in which athird isolation structure is formed which isolates the parts of thefirst doped zone, the second gate electrode and the diode structure oneither side of the fifth trench from one another, sixth trenches areproduced which cross the first trenches, the second trenches and thirdtrenches, which extend down into the first doped zone without cuttingthrough the first doped zone and which are filled with fourth isolationstructures, word lines are produced which extend parallel to the sixthtrenches and which are connected in an electrically conducting manner tothe first gate electrodes via word-line contacts, adjacent memory cellsare arranged in a mirror-symmetrical manner along a word line, and ineach case, that part of the first doped zone that is disposed betweenthe first trench and the third trench is connected as bit line and thatpart of the first doped zone that is disposed between the third trenchand the second trench is connected as supply-voltage line.

In the method according to the invention, a silicon substrate isprovided with a vertical sequence of doped zones which comprises atleast a first doped zone, a second doped zone and a third doped zone forsource zone, channel zone and drain zone of vertical MOS transistors. Inthe vertical sequence of doped zones, a selection transistor and amemory transistor are formed by etching trenches which extend in eachcase down into the first zone and by providing the surface of thetrenches with a gate dielectric and a gate electrode in each case.

A further trench which cuts through the first doped zone, the seconddoped zone and the third doped zone is produced between the twotrenches. An isolation structure which separates the first doped zoneand the second doped zone into two parts which are isolated from oneanother in each case is formed in the trench. Those parts of the thirddoped zone that are separated by the further trench are electricallyinterconnected by an interconnect structure.

A diode structure is produced with one terminal is connected in anelectrically conducting manner to the third doped zone and anotherterminal connected in an electrically conducting manner to one of thegate electrodes.

In this arrangement, the memory transistor is formed by the first dopedzone, the second doped zone, the third doped zone and the gate electrodeconnected to the diode structure. The selection transistor is formed bythe other gate electrode, the first doped zone, the second doped zoneand the third doped zone. The third doped zone, together with theinterconnect structure, forms the common source/drain zone of theselection transistor and the memory transistor. The diode structure isdimensioned in such a way that a relatively high current flow occursduring charging and a relatively low current flow occurs when thecapacitance which is active at the gate electrode of the memorytransistor discharges.

In a matrix-type arrangement of a multiplicity of memory cells, thatpart of the first doped zone that belongs to the selection transistorforms a bit line, while that part of the first doped zone that belongsto the memory transistor forms a supply-voltage line. Both the bit lineand the supply-voltage line are buried in the structure and do not needany additional area.

In the matrix-type arrangement of the memory cells, word lines, whichcross the bit lines and the supply-voltage lines, are produced on thesurface of the structure. Adjacent memory cells along a word line arepreferably of a mirror-symmetrical design, every two immediatelyadjacent memory cells having a common wordline contact.

Preferably, a silicon substrate is used which is doped with a firstconductivity type. To form the first doped zone, a silicon layer that isdoped with a second conductivity type opposite to the first is grownepitaxially thereon. To form the second doped zone, a silicon layerdoped with the first conductivity type is applied by LPCVD epitaxy or bymolecular-beam epitaxy. To form the third doped zone, a silicon layerdoped with the second conductivity type is applied by LPCVD epitaxy orby molecular-beam epitaxy. LPCVD epitaxy is an abbreviation forlow-pressure chemical vapour deposition.

It is within the scope of the invention to form the diode structure as aSchottky diode in such a way that a low resistance value occurs duringcharging and a high resistance value occurs when the capacitance activeat the gate electrode discharges. For this purpose, the gate electrodeis formed, for example, from doped polysilicon and a layer of a metal,for example aluminium, is deposited thereon.

Alternatively, the diode structure is formed as an n⁺ -p diode. For thispurpose, the second gate electrode is preferably formed from dopedpolysilicon and is provided with a suitably doped polysilicon structure.The doped polysilicon structure and the gate electrode are the commondiode structure. This embodiment is preferred with a view to integrationin existing VLSI technologies. To simplify the subsequent contactingbetween the doped polysilicon structure and the third doped zone, it iswithin the scope of the invention to provide the surface of the dopedpolysilicon structure with a metal silicide layer. The metal silicidelayer is preferably produced in a self-aligning process.

The dopant concentration in the first doped zone and in the third dopedzone, which each form source/drain regions of the MOS transistors, ishigh, with a dopant concentration of more than 10¹⁹ cm⁻³, while thedopant concentration in the second doped zone, which forms a channelzone, is adjusted to less than, or equal to 10¹⁸ cm⁻³. To form the firstand second gate dielectrics, a thermal oxidation is carried out at 700°to 800° C. In this process, the gate dielectric forms on the moreheavily doped zones with a thickness which is a multiple of that of themore lightly doped zone used as a channel region. The greater thicknessof the gate dielectric at the surface of the source/drain zones bringsabout a reduction in the overlap capacitances.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is explained in greater detail below by reference to anexemplary embodiment and the figures.

FIG. 1 is a side cross section which shows a silicon substratecontaining a vertical sequence of doped zones.

FIG. 2 is a side cross section which shows the silicon substrate afterthe formation of trenches which are each provided with gate dielectricand gate electrode for a selection transistor and a memory transistor.

FIG. 3 is a side cross section which shows the silicon substrate afterthe formation of a diode structure.

FIG. 4 is a side cross section which shows the silicon substrate afterthe formation of isolating trenches between the selection transistor andthe memory transistor, and also with respect to adjacent memory cells.

FIG. 5 is a side cross section which shows the silicon substrate afterformation of an interconnect structure between the third doped zone anda diode structure.

FIG. 6 is a side cross section which shows the silicon substrate afterthe formation of word-line contacts.

FIG. 7 is a plan view of a memory-cell arrangement produced according tothe invention.

FIG. 8 is an equivalent circuit diagram of a memory cell produced by themethod according to the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An n⁺ -doped layer 2 having a dopant concentration of, for example,3×10¹⁹ cm⁻³ is grown epitaxially on a silicon substrate 1 which is, forexample, p-doped with a dopant concentration of 10¹⁶ cm⁻³ (see FIG. 1).The first doped silicon layer 2 is applied in a thickness of, forexample, 300 nm.

A second doped silicon layer 3 which is, for example, p-doped with adopant concentration of 8×10¹⁷ cm⁻³ is applied to the first dopedsilicon layer 2 and a third doped silicon layer 4 which is, for example,n⁺ -doped with a dopant concentration of 3×10¹⁹ cm⁻³ is applied thereto.The second doped silicon layer 3 and the third doped silicon layer 4 areproduced in a thickness of, in each case, approximately 150 nm with theaid of epitaxial methods such as LPCVD epitaxy or molecular-beamepitaxy. The LPCVD epitaxy (that is an abbreviation for low-pressurechemical vapour deposition) is carried out, for example, using silaneand diborane or arsine in the temperature range from 700° to 900° C. andin the pressure range from 2 to 20 mbar. The molecular-beam epitaxy ispreferably carried out in the temperature region of 520° C. and in thepressure region of 5×10⁻¹⁰ mbar.

Using a mask (not shown), a first trench 5 and a second trench 6 whicheach extend down into the first doped layer 2 (see FIG. 2) are producedby anisotropic etching. By thermal oxidation at 700° to 800° C., a firstgate dielectric 7 composed of SiO₂ is produced at the walls and thefloor of the first trench 5 and a second gate dielectric 8 composed ofSiO₂ is produced at the walls and the floor of the second trench 6.Owing to the dopant concentration in the first doped layer 2, the seconddoped layer 3 and the third doped layer 4, the first gate dielectric 7and the second gate dielectric 8 grow at the surface of the second dopedlayer 3 with a thickness which is in each case approximately one thirdless than at the surface of the first doped layer 2 and the third dopedlayer 4. By filling with polysilicon which is n⁺ -doped in situ, a firstgate electrode 9 is produced in the first trench 5 and a second gateelectrode 10 is produced in the second trench 6.

The second gate electrode 10 is back-etched so that it terminates inheight approximately at the level of the second doped layer 3 (see FIG.3). In this process, the remaining surface is protected against etchattack by a mask (not shown). A diffusion-barrier layer 10a is appliedto the second gate electrode 10. The diffusion-barrier layer 10a isformed from a very thin oxide layer having a thickness of, for example,1 nm or a very thin silicide layer having a thickness of, for example, 2nm. A doped polysilicon structure 11, which essentially fills the secondtrench, is then produced in the second trench 6 by filling it withp-type polysilicon doped in situ. The diffusion-barrier layer 10a on thesurface of the second gate electrode 10 prevents an outdiffusion of thedopants of the doped polysilicon structure 11 into the second gateelectrode 10.

To simplify the subsequent contacting, the doped polysilicon structure11 is provided with a self-aligning metal silicide layer 12 as shown inFIG. 3. A third trench 13 as shown in FIG. 4, which extends down intothe substrate 1, is produced between the first trench 5 and the secondtrench 6. The third trench 13 cuts through the first doped layer 2, thesecond doped layer 3 and also the third doped layer 4. The third trench13 is provided with a first isolation structure 14 composed, forexample, of SiO₂ and extending at least up to the height of the seconddoped layer 3 (see FIG. 4).

Simultaneously, a fourth trench 15 is produced inside the first trench 5and a fifth trench 16 inside the second trench 6. The fourth trench 15and the fifth trench 16 each extend down into the substrate 1 and ineach case cut through the first doped layer 2 below the first trench 5or second trench 6, respectively.

The fourth trench 15 is provided with a second isolation structure 17,for example, composed of SiO₂ which extends in height up into the firstgate electrode 9. Free space left above the latter in the fourth trench15 is filled with an n⁺ -doped polysilicon structure 18 whichelectrically interconnects parts of the first gate electrode 9 which areseparated by the fourth trench 15.

The fifth trench 16 is provided with a third isolation structure 19composed, for example, of SiO₂ and completely filling the fifth trench16. The third isolation structure 19 in the fifth trench 16 cuts thesecond gate electrode 10, the diffusion-barrier layer 10a, the dopedpolysilicon structure 11 and the metal silicide layer 12 into two partswhich are isolated from one another in each case.

In the third trench 13, an interconnect structure 20 which is composed,for example, of n-doped polysilicon and which electrically interconnectsparts of the third doped layer 4 separated by the third trench 13 isproduced above the first isolation structure 14. Preferably, theinterconnect structure 20 terminates level with the surface of the thirddoped layer 4.

Those parts of the first doped layer 2, second doped layer 3, thirddoped layer 4, the first gate dielectric 7 and the first gate electrode9 that are disposed between the third trench 13 and the fourth trench 15form a selection transistor. Those parts of the first doped layer 2,second doped layer 3, third doped layer 4, the second gate dielectric 8and the second gate electrode 10 that are disposed between the thirdtrench 13 and the fifth trench 16 form a memory transistor. Theselection transistor and the memory transistor have a commonsource/drain zone formed by the corresponding parts of the third dopedlayer 4 and the interconnect structure 20. Incidentally, the selectiontransistor and the memory transistor are separated from one another bythe first isolation structure 14. The memory cell is bounded laterallyby the fourth trench 15 and the fifth trench 16. Memory cells which aredisposed in mirror-image fashion in each case but are otherwise ofanalogous structure adjoin the fourth trench 15 and the fifth trench 16.

The doped polysilicon structure 11 and the second gate electrode 10 forma p-n⁺ diode which, in this exemplary embodiment, forms a diodestructure connected between the common source/drain zone 4, 20 and thesecond gate electrode 10. For the purpose of electrical connectionbetween the p-n⁺ diode 10, 11, a polysilicon strip 21 (see FIG. 5) isproduced which is, for example, n-doped and which is connected both tothe surface of the metal silicide layer 12 and to the third doped layer4 between the third trench 13 and the fifth trench 16 (see FIG. 5).

The third trench 13, the fourth trench 15 and the fifth trench 16 extendthrough the entire memory cell arrangement perpendicularly to the planeof the drawing. Sixth trenches are produced which extend transversely tothe third trench 13, the fourth trench 15 and the fifth trench 16 andwhich extend down into the first doped layer 2, for example 100 runbelow the interface with the second doped layer 3, and which are filledwith fourth isolation structures 22 (see FIG. 7). The sixth trenchesextend, for example, at a right angle to the third trenches 13 outsidethe plane of the drawing shown in FIGS. 5 and 6. The depth of the sixthtrenches is shown as a broken line 23 in FIGS. 5 and 6. The fourthisolation structure 22 isolates adjacent selection transistors or memorytransistors along the third trench 13. At the same time, selectiontransistors disposed between the third trench 13 and the fourth trench15 are electrically interconnected by that part of the first doped layerthat is disposed between the third trench 13 and the fourth trench 15and below the sixth trench 23 and that acts as bit line 2a as shown inFIG. 5.

Memory transistors disposed between the third trench 13 and the fifthtrench 16 are electrically interconnected via that part of the seconddoped layer that is disposed between the third trench 13 and the fifthtrench 16 below the sixth trench 23 and which forms a common supply line2b.

A passivation layer 24 as shown in FIG. 6, which is produced, forexample, from TEOS/SiO₂, is applied over the entire surface. Vias to thefirst gate electrodes 9 are opened in the passivation layer 24 and areprovided with a word-line contact 25 by filling with a suitable metal,for example tungsten. At the same time, the first gate electrodes 9 ofadjacent memory cells disposed in the same first trench 5 are providedwith a common word-line contact 25 (see FIG. 6). The word-line contacts25 are interconnected, for example, with the aid of an aluminiummetallization (not shown).

The buried bit lines 2a and the supply-voltage lines 2b are connected toappropriate voltages at spacings, which are substantially greater thanthe grid dimension of the memory cells, with the aid of vias.

Since the diode structure in this memory cell is formed as a p-njunction which is disposed as upper layer in each case in the secondtrench 6, the diode structure can be processed in planar manufacturingsteps without the total area of the memory cell thereby being increased.

The area requirement of the memory cells produced by the productionmethod according to the invention is furthermore minimized by the factthat the bit lines 2a and the supply-voltage lines 2b are buried in thelayer structure. As a result, further interconnect levels for bit linesor feeding the supply voltage become superfluous.

Since adjacent memory cells disposed along the sixth trenches are ineach case of mirror-symmetrical design, the buried bit lines 2a extendin bit-line pairs. In this design, therefore, both "open" and "folded"bit-line architectures may be formed.

As a departure from the example described above, an SiO₂ layer may beapplied in a thickness of approximately 500 to 800 run for the purposeof subsequent isolation of the transistors after the epitaxialapplication of the first doped layer 2. Holes for the active transistorzones which are filled in each case with the second doped layer and thethird doped layer by selective epitaxy are etched in the SiO₂ layer. Inthis variant, the structured SiO₂ layer replaces the isolationstructures 14, 17 and 19.

FIG. 7 shows a plan view of a memory-cell arrangement produced accordingto the invention. In this example, the sixth trenches filled in eachcase with the fourth isolation structure 22 extend perpendicularly tothe third trenches 13. However, the trenches may also intersect at anyother desired angle. Disposed alongside one another in each case betweenadjacent sixth trenches are a word-line contact 25 which belongs to twoadjacent memory cells, the first gate electrode 9, the first gatedielectric 7, a part of the third doped silicon layer 4, the thirdtrench 13, the doped polysilicon strip 21 and the fifth trench 16 whichin turn belongs jointly to adjacent memory cells. The area of a singlememory cell 26 is shown in FIG. 7 as a chain-dot line.

FIG. 8 shows an equivalent circuit diagram of a memory cell. The memorycell comprises a selection transistor AT and a memory transistor STwhich are connected in series between a bit line BL and a supply-voltageline V_(DD) via a common source/drain zone. A diode structure D isconnected between the common source/drain zone and the gate electrode ofthe memory transistor ST in such a way that a low resistance valueoccurs when a capacitance which is active at the gate electrode of thememory transistor charges and a high resistance value occurs when itdischarges. The gate electrode of the selection transistor AT isconnected to a word line WL. The operation of such a memory cell isdescribed in International published patent application WO 92/01287which claims a common priority with U.S. Pat. No. 5,327,374 and, towhich reference is made in relation to the method of operation.

Although other modifications and changes may be suggested by thoseskilled in the art, it is the intention of the inventors to embodywithin the patent warranted hereon all changes and modifications asreasonably and properly come within the scope of their contribution tothe art.

We claim:
 1. A method of producing an arrangement containingself-amplifying dynamic MOS transistor memory cells, comprising thesteps of;providing a silicon substrate with a vertical sequence of dopedzones which comprises at least a first doped zone a second doped zonedisposed thereon and a third doped zone disposed thereon for a sourcezone, a channel zone and a drain zone of vertical MOS transistors,etching a first trench and a second trench down into the first zone andwhich traverse the second zone and the third zone, providing a surfaceof the first trench with a first gate dielectric and a surface of thesecond trench with a second gate dielectric, forming a first gateelectrode in the first trench and forming a second gate electrode in thesecond trench, producing a third trench which cuts through the firstdoped zone, the second doped zone and the third doped zone between thefirst trench and the second trench, providing the third trench with afirst isolation structure at least in a region of the first doped zoneand of the second doped zone, electrically interconnecting parts of thethird doped zone that are separated by the third trench by aninterconnect structure, and producing a diode structure whose oneterminal is connected in an electrically conducting manner to the thirddoped zone and whose other terminal is connected in an electricallyconducting manner to that of the second gate electrode.
 2. A methodaccording to claim 1, further comprising the steps of:doping the siliconsubstrate with a first conductivity type, said first doped zone beingprovided by epitaxially growing a silicon layer doped with a secondconductivity type opposite to the first conductivity type on the siliconsubstrate, said second doped zone being provided by applying a siliconlayer doped with the first conductivity type by one of low-pressurechemical vapour deposition epitaxy and molecular-beam epitaxy, and saidthird doped zone being provided by applying a silicon layer doped withthe second conductivity type by one of LPCVD epitaxy and molecular-beamepitaxy.
 3. A method according to claim 1, wherein the diode structureis formed as a Schottky diode.
 4. A method according to claim 1, whereinthe diode structure is formed as an n⁺ -p diode.
 5. A method accordingto claim 4, whereinthe second gate electrode is formed from dopedpolysilicon, a doped polysilicon structure is produced which, with thesecond gate electrode, is the diode structure, and the doped polysiliconstructure is connected in an electrically conducting manner to the thirddoped zone.
 6. A method according to claim 5, whereinthe second gateelectrode is produced in the second trench in a height essentiallycorresponding to the level of the second doped zone, the dopedpolysilicon structure is produced in the second trench above the secondgate electrode, a surface of the doped polysilicon structure is providedwith a metal silicide layer, a doped polysilicon strip is produced inwhich the metal silicide layer and the third doped zone overlap at leastpartly in each case.
 7. A method according to claim 5, furthercomprising the step of,producing a diffusion-barrier layer between thesecond gate electrode and the doped polysilicon structure.
 8. A methodaccording to one of claims 1, whereina dopant concentration in the firstdoped zone and in the third doped zone is in the range greater than orequal to 10¹⁹ cm⁻³, a dopant concentration in the second doped zone isin the range less than or equal to 10¹⁸ cm⁻³, the first gate dielectricand the second gate dielectric are formed by thermal oxidation at 700°to 800° C.
 9. A method according to claim 1, wherein the interconnectstructure is formed by the third trench composed of doped polysilicon ofthe same conductivity type as the third doped zone.
 10. A methodaccording to claim 1, further comprising the steps of:forming amultiplicity of memory cells disposed in matrix fashion in the siliconsubstrate, the first trench, the second trench and the third trench areeach formed as parallel strips, producing inside the first trench, afourth trench which cuts through the first doped zone and in which asecond isolation structure is formed which isolates at least parts ofthe first doped zone on either side of the fourth trench from oneanother, producing inside the second trench, a fifth trench which cutsthrough the first doped zone and in which a third isolation structure isformed which isolates parts of the first doped zone, the second gateelectrode and the diode structure on either side of the fifth trenchfrom one another, producing sixth trenches which cross the firsttrenches, the second trenches and third trenches, which extend down intothe first doped zone without cutting through the first doped zone andwhich are filled with fourth isolation structures, producing word lineswhich extend parallel to the sixth trenches and which are connected inan electrically conducting manner to the first gate electrodes viaword-line contacts, adjacent ones of said multiplicity of memory cellsbeing arranged in a mirror-symmetrical manner along a word line,connecting a part of the first doped zone that is disposed between thefirst trench and the third trench as a bit line and that part of thefirst doped zone that is disposed between the third trench and thesecond trench as supply-voltage line.